1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a method for laying-out a semiconductor integrated circuit. More particularly, the present invention relates to a master slice type semiconductor integrated circuit and a method for laying-out thereof.
2. Description of the Related Art
Conventionally, a master slice type semiconductor integrated circuit is known. According to the master slice type semiconductor integrated circuit, a master slice in which a plurality of cells with basic function such as logical gates, flip-flops and so on are formed on a semiconductor chip is prefabricated. After that, a wiring pattern for realizing a desired logic circuit requested by a customer is determined.
FIG. 1 is a plan view schematically showing an example of a configuration of such a master slice type semiconductor integrated circuit. As shown in FIG. 1, the semiconductor integrated circuit 100 has a plurality of cells 102 such as flip-flops which are arranged on a semiconductor chip 101. Also, a “clock tree” based on Clock Tree Synthesis (CTS) is arranged on the semiconductor chip 101, which distributes clock signals to respective of the plurality of cells 102. The clock signal is generated by a clock generating circuit such as a PLL (Phase Locked Loop) 103 and supplied to the clock tree on the semiconductor chip 101. The clock tree is configured to distribute the clock signal from a plurality of first clock buffers 104 in the center of the semiconductor chip 101 to a plurality of second clock buffers 106 through clock wirings 105. Similarly, a plurality of third clock buffers (not shown) may be arranged in order to distribute the clock signals from the second clock buffers 106. Eventually, the clock signals are distributed to respective of the plurality of cells 102.
Another master slice type semiconductor integrated circuit is disclosed in Japanese Laid Open Patent Application (JP-P2003-152082A). In the semiconductor integrated circuit, sequential circuit cells and combinational circuit cells are arranged in an inner core region on a semiconductor chip. The inner core region is sectioned into a plurality of regions. In order to selectively distribute multi-phase clock signals to each of the sectioned regions, a clock tree structure with the same load and the same wiring length is formed by using a plurality of first selectors, a plurality of second selectors and a plurality of third selectors. Each of the selectors selects any one of a plurality of inputted clock signals and outputs the selected clock signal, and hence one clock signal is distributed to desired one of the sectioned regions.
FIG. 2 is a circuit diagram showing a part of a clock tree structure according to the semiconductor integrated circuit 200 disclosed in the above document. Multi-phase clock signals CLK_A˜CLK_H are externally supplied to each of first multiplexers MC101˜MC104 (the first selectors). An output of each of the first multiplexers MC101˜MC104 is distributed to each of second multiplexers MC201˜MC204 (the second selectors). An output of each of the second multiplexers MC201 and MC202 is distributed to each of third multiplexers MC301 and MC302 (the third selectors), and an output of each of the second multiplexers MC203 and MC204 is distributed to each of third multiplexers MC303 and MC304 (the third selectors).
Here, three external control signals S0, S1 and S2 are supplied to each of the first multiplexers MC101˜MC104, two external control signals S0 and S1 are supplied to each of the second multiplexers MC201˜MC204, and an external control signal S0 is supplied to each of the first control signal S0. Thus, each of the first multiplexers MC101˜MC104, the second multiplexers MS201˜MC204 and the third multiplexers MC301˜MC304 operates as a selector, selects any one of the clock signals CLK_A˜CLK_H and outputs the selected clock signal. It should be noted that the external control signals inputted to respective multiplexers are controlled independently to be able to have different signal values.
For example, one of the first multiplexers MC101˜MC104 selects and outputs the clock signal CLK_A when “000” are given as the three external control signals S0, S1 and S2, selects and outputs the clock signal CLK_B when “001” are given as the three external control signals S0, S1 and S2, and selects and outputs the clock signal CLK_C when “010” are given as the three external control signals S0, S1 and S2. Also, one of the second multiplexers MC201˜MC204 selects and outputs the first input signal (for example, a clock signal from MC101 in the case of MC201) when “00” is given as the two external control signal S0 and S1, selects and outputs the second input signal (for example, a clock signal from MC102 in the case of MC201) when “01” is given as the two external control signal S0 and S1, and selects and outputs the third input signal (for example, a clock signal from MC103 in the case of MC201) when “10” is given as the two external control signal S0 and S1. Also, one of the third multiplexers MC301˜MC304 selects and outputs the first input signal (for example, a clock signal from MC201 in the case of MC301) when “0” is given as the one external control signal S0, and selects and outputs the second input signal (for example, a clock signal from MC202 in the case of MC301) when “1” is given as the one external control signal S0.
Then, a clock signal which is selected by the multiplexers as mentioned above is distributed to any of the sectioned regions. For example, the clock signal CLK_A or CLK_B is selectively distributed to the sectioned regions (Area1 and Area2). The clock signal CLK_C or CLK_D is selectively distributed to the sectioned regions (Area3 and Area4). Each of these clock signals CLA_A˜CLK_D is supplied to sequential circuit cells which are arranged in corresponding one of the sectioned regions.
There are problems with the above-mentioned conventional semiconductor integrated circuit in that clock skew between cells and electric power consumption increase since the multi-phase clock signals are distributed to all over the semiconductor chip. This problem still exists even if a clock tree is used between a clock input terminal and a clock output terminal (an input of each cell).
More specifically, according to the master slice type semiconductor integrated circuit 100 shown in FIG. 1, the clock signal has to be distributed to all over the semiconductor chip 101. Thus, as the area of the semiconductor chip 101 becomes wider, the clock wiring 105 becomes longer and the number of the clock buffers becomes larger, which causes the increase in electric power consumption. Moreover, as the number of steps of the clock buffer increases, the clock signal becomes more susceptible to dispersion of characteristics of transistors in the clock buffer, which causes larger clock skew.
According to the master slice type semiconductor integrated circuit 200 having the clock tree structure shown in FIG. 2, each of the first multiplexers MC101˜MC104, the second multiplexers MC201˜MC204 and the third multiplexers MC301˜MC304 in the clock tree is configured to operate as a selector, namely, to select and output any one of the inputted clock signals. However, similar to the former master slice type semiconductor integrated circuit 100, there is still a problem that clock skew and electric power consumption increase as the semiconductor chip becomes larger.